1. Field of the Invention
The present invention relates to the field of digital computer systems, and more particularly, to a bus interface (a bridge) between two busses.
2. Description of Related Art
In computer systems, electronic chips and other components are connected with one another by buses. A variety of components can be connected to the bus providing intercommunication between all of the devices that are connected to the bus. One type of bus which has gained wide industry acceptance is the industry standard architecture (ISA) bus. The ISA bus has twenty-four (24) memory address lines which therefore provides support for up to sixteen (16) megabytes of memory. The wide acceptance of the ISA bus has resulted in a very large percentage of devices being designed for use on the ISA bus. However, higher-speed input/output devices commonly used in computer systems require faster buses.
A solution to the general problem of sending and receiving data from the processor to any high-speed input device is a local bus. Unlike the ISA bus, which operates relatively slowly with limited bandwidth, a local bus communicates at system speed and carries data in 32-bit blocks. Local bus machines remove from the main system bus those interfaces that need quick response, such as memory, display, and disk drives. One such local bus that is gaining acceptance in the industry is the peripheral component interconnect (PCI) bus. The PCI bus can be a 32 or 64-bit pathway for high-speed data transfer. Essentially, the PCI bus is a parallel data path provided in addition to an ISA bus. The system processor and memory can be attached directly to the PCI bus, for example. Other devices such as graphic display adapters, disk controllers, sound cards, etc. can also attach directly or indirectly (e.g., through a host bridge) to the PCI bus.
A bridge chip is provided between the PCI bus and the ISA bus in order to provide communication between devices on the two buses. The bridge chip essentially translates the ISA bus cycles to PCI bus cycles, and vice versa.
Many of the devices attached to the PCI bus and the ISA bus are "master" devices that can conduct processing independently of the bus or other devices. Certain devices coupled to the buses are considered to be "slaves" or "targets" that accept commands and respond to requests of a master. Many devices are able to serve as both a master and a slave in certain circumstances.
It is desirable to provide the bridge chip between the PCI bus and the ISA bus with certain functionality, such as scatter/gathering, integrated drive electronics (IDE) interfacing, PCI arbitration, etc. For at least some of these purposes, the bridge chip contains slaves. These slaves need to respond to the PCI bus according to the PCI bus protocol, set forth in the PCI Specification, herein expressly incorporated by reference. However, to provide the desired functionality in the bridge chip within the specified response time required by the PCI bus is problematical if the bridge chip is implemented in a relatively inexpensive and slower technology, such as a 0.8 micron CMOS technology. The problem arises due to the need to latch the signals that are received from the PCI bus as inputs to the bridge chip as well as those signals sent to the PCI bus from the bridge chip to allow the slaves implemented in the slower technology to make use of the signals. The two clock latency created by the latching is incompatible with the PCI bus protocol.